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83 lines
2.6 KiB
83 lines
2.6 KiB
8 years ago
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// Created by MightyPork on 2017/02/17.
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//
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#ifndef STM8S_FNCGEN_H
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#define STM8S_FNCGEN_H
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// See the C file for doxygen
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#include "stm8s.h"
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// Freq write - addr + 14 bits
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// B28 and HLB allow sequential write, or repeated update of half-registers
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// In sequential write, the half-registers are written in the order LSB, MSB
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#define FG_ADDR_CR (u16)0x0000
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#define FG_ADDR_FREQ0 (u16)0x4000
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#define FG_ADDR_FREQ1 (u16)0x8000
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// Phase write - addr + 12 bits
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#define FG_ADDR_PHASE0 (u16)0xC000
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#define FG_ADDR_PHASE1 (u16)0xE000
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#define FG_B28 (u16)0x2000 // Enable sequential write of the freq registers
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#define FG_HLB (u16)0x1000 // Nonsequential write, register select (0-LSB, 1-MSB)
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#define FG_FSELECT (u16)0x0800 // Select active frequency reg
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#define FG_PSELECT (u16)0x0400 // Select active phase reg
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#define FG_RESET (u16)0x0100 // Reset counter and keep output at midpoint
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#define FG_SLEEP1 (u16)0x0080 // Suspend
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#define FG_SLEEP12 (u16)0x0040 // Shut down ADC (when using square output)
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#define FG_OPBITEN (u16)0x0020 // Output counter MSb (0=SIN/TRI,1=SQUARE)
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#define FG_DIV2 (u16)0x0008 // Divide counter MSb by 2
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#define FG_MODE (u16)0x0002 // If ADC enabled, 0 = SIN, 1 = TRI
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/** Convert frequency in Hz to a register value (for 25 MHz MCLK) */
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#define HZ_REG(hz) (u32)((float)hz * 10.73741824f)
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/** Function generator instance object */
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typedef struct {
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uint16_t CREG;
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GPIO_TypeDef *NSS_GPIO;
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GPIO_Pin_TypeDef NSS_PIN;
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} FG_Instance;
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/** FG frequency bank number */
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typedef enum {
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FREQ0 = 0,
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FREQ1 = 1
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} FG_FreqBank;
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/** FG phase bank number */
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typedef enum {
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PHASE0 = 0,
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PHASE1 = 1
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} FG_PhaseBank;
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/**
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* Function generator waveform presets
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*/
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typedef enum {
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WFM_SINE = (u16) 0,
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WFM_TRIANGLE = (u16) FG_MODE,
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WFM_SQUARE = (u16) (FG_OPBITEN | FG_DIV2),
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WFM_SQUARE_DIV2 = (u16) FG_OPBITEN
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} FG_Waveform;
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void FG_JoinBroadcast(FG_Instance *inst);
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void FG_LeaveBroadcast(FG_Instance *inst);
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void FG_SetFreq(FG_Instance *inst, FG_FreqBank bank, u32 regval);
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void FG_SetFreqMSB(FG_Instance *inst, FG_FreqBank bank, u16 msb14);
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void FG_SetFreqLSB(FG_Instance *inst, FG_FreqBank bank, u16 lsb14);
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void FG_FreqSwitch(FG_Instance *inst, FG_FreqBank bank);
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void FG_SetPhase(FG_Instance *inst, FG_PhaseBank bank, u16 regval);
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void FG_PhaseSwitch(FG_Instance *inst, FG_PhaseBank bank);
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void FG_SetWaveform(FG_Instance *inst, FG_Waveform wfm);
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void FG_Suspend(FG_Instance *inst);
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void FG_Resume(FG_Instance *inst);
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void FG_Cmd(FG_Instance *inst, FunctionalState enable);
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void FG_Reset(FG_Instance *inst);
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void FG_Init(FG_Instance *inst, GPIO_TypeDef *NSS_GPIO, GPIO_Pin_TypeDef NSS_PIN);
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void FG_SPI_Init(void);
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#endif //STM8S_FNCGEN_H
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