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60 lines
1.1 KiB
60 lines
1.1 KiB
9 years ago
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;;;-------------------------------------------------
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;; Configure the system clock & flash timing
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;;
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;; Code for L100, 16 Mhz HSI, configure flash prefetch etc.
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;;
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Cfg_RCC PROC
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PUSH {R0, R1, R2, LR}
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; Flash timing - 64-bit access, pre-fetch, latency = 1
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; Pozor! ACC64 a (PRFTEN|LATENCY) nejde zapsat najednou!
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; 64-bit access
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LDR R2, =FLASH_ACR
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LDR R1, [R2]
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LDR R0, =FLASH_ACR_ACC64
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ORR R1, R0
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STR R1, [R2]
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; Frefetch, Latency
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LDR R0, =(FLASH_ACR_PRFTEN :OR: FLASH_ACR_LATENCY)
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ORR R1, R0
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STR R1, [R2]
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; Power on HSI (runs from MSI on start)
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LDR R2, =RCC_CR
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LDR R1, [R2]
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LDR R0, =RCC_CR_HSION
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ORR R1, R0
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STR R1, [R2]
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; Wait for HSIRDY
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LDR R0, =RCC_CR
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HsyWait LDR R1, [R0]
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TST R1, #RCC_CR_HSIRDY
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BEQ HsyWait
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; Select HSI as the core clock source
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LDR R2, =RCC_CFGR
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LDR R1, [R2]
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; clear RCC_CFGR_SW
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LDR R0, =RCC_CFGR_SW
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BIC R1, R0
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; write RCC_CFGR_SW_HSI
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ORR R1, #2_01
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STR R1, [R2]
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POP {R0, R1, R2, PC}
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ENDP
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;;
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;;;-------------------------------------------------
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END
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