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85 lines
1.9 KiB
85 lines
1.9 KiB
9 years ago
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;;;-------------------------------------------------
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;; Configure the system clock & flash timing
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;;
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;; Code for F303RE, clock set to 48 MHz from HSI
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;;
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;; Different speed (16 MHz, 72 MHz) can be achieved
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;; by changing the value of PLL_MUL in RCC_CFGR.
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;;
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;; !!! if changing speed to 72 MHz, Flash latency must
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;; be changed to 2 wait states - see reference manual.
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;;
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Cfg_RCC PROC
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PUSH {R0, R1, R2, LR}
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; --- Flash timing config ---
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; Frefetch, Latency
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LDR R2, =FLASH_ACR
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LDR R1, =(FLASH_ACR_PRFTBE :OR: (1 << FLASH_ACR_LATENCY_ofs))
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STR R1, [R2]
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; --- Internal High-speed Oscillator ---
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; Power on HSI (runs from MSI on start)
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LDR R2, =RCC_CR
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LDR R1, [R2]
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ORR R1, #RCC_CR_HSION
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STR R1, [R2]
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; Wait for HSIRDY
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LDR R0, =RCC_CR
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HsyWait LDR R1, [R0]
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TST R1, #RCC_CR_HSIRDY
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BEQ HsyWait
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; --- PLL to get higher frequency ---
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; Set up PLL
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LDR R2, =RCC_CFGR
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LDR R1, =0
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ORR R1, #(2_100 << RCC_CFGR_PPRE2_ofs) ; PPRE2 divided by 2 (AHB, APB1 not divided - zero)
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ORR R1, #(1 << RCC_CFGR_PLLSRC_ofs) ; PPLSRC = HSI
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ORR R1, #(2_0100 << RCC_CFGR_PLLMUL_ofs) ; PLL_MUL -> 8MHz x6 = 48MHz
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STR R1, [R2]
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; Power on PLL
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LDR R2, =RCC_CR
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LDR R1, [R2]
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ORR R1, #RCC_CR_PLLON
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STR R1, [R2]
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; Wait for PLLRDY
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LDR R0, =RCC_CR
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PllWait LDR R1, [R0]
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TST R1, #RCC_CR_PLLRDY
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BEQ PllWait
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; --- Select PLL as source ---
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; write 0b10 to RCC_CFGR_SW
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; Select PLL as the core clock source
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LDR R2, =RCC_CFGR
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LDR R1, [R2]
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; clear field
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LDR R0, =RCC_CFGR_SW
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BIC R1, R0
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; select PLL
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LDR R0, =(2_10 << RCC_CFGR_SW_ofs)
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ORR R1, R0
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; save
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STR R1, [R2]
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; TODO: should now wait for the switch (SWS == SW)
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POP {R0, R1, R2, PC}
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ENDP
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;;
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;;;-------------------------------------------------
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END
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